ADR-003: Wave v2 FPGA Strategy (ECP5)
Status: Accepted Date: November 2025 Related: See ADR-001-wave-v2-architecture.md for complete system architecture
Decision Summary
Selected: Include Lattice ECP5 FPGA despite MCU having sufficient DSP capability
Justification: FPGA provides architectural benefits and enables premium features that unlock 50–100% larger addressable market for only 6% COGS increase.
Why Include FPGA? ($20–25 Cost Analysis)
Core Architectural Benefits (v2.0 - Day 1)
1. Clean Multi-Chip SPI Aggregation
- FPGA as single SPI master to 3× AMC131M03
- Aggregates 9 channels, presents unified interface to MCU
- Alternative (no FPGA): MCU manages 3 separate SPI buses
- More complex firmware, harder to debug
- Timing coordination challenges
- Shared SPI bus (daisy-chain) adds latency
Value: Architectural simplicity, deterministic timing
2. Hardware Digital Rogowski Integration
- Real-time integration at 32 kHz with < 1 μs latency
- Alternative (MCU): Interrupt-driven at 32 kHz
- 128k interrupts/sec load on MCU
- Jitter from OS scheduling, other interrupts
- Works, but less deterministic
Value: Offloads MCU, guaranteed real-time performance
Premium Features (Optional Modules - v2.1+)
3. GPS Timestamping for Synchrophasor (IEEE C37.118)
Application: Synchrophasor measurement units (PMU) for utility grid management
- Compare phase angle across distributed substations
- Requirement: Phase angle accuracy <0.573° = ~26 μs @ 60 Hz
- To achieve this: < 1 μs timestamping precision
With FPGA:
GPS PPS (1 Hz) → FPGA counter @ 100 MHz → Latch ADC sample timestamp
Precision: 10 ns (100 MHz clock)
Jitter: < 100 ns (deterministic hardware)
Without FPGA (MCU GPIO interrupt):
GPS PPS → MCU interrupt → Read timestamp → Associate with sample
Jitter: 1–10 μs (interrupt latency, OS scheduling, cache misses)
Result:
- FPGA enables IEEE C37.118 compliance (utility synchrophasor applications)
- MCU-only fails spec by ~10× (adequate for coarse time sync, but not PMU-grade)
Market value: Utilities pay 2–5× premium for C37.118-compliant PMUs vs standard power quality monitors
4. EtherCAT Deterministic Control
Application: Industrial automation real-time control loops
- Requirement: EtherCAT cycle time 1 ms with < 100 μs jitter
- Control loop: Read sensor → Calculate setpoint → Write to actuator (VFD, active filter)
With FPGA:
ADC → FPGA preprocessing → EtherCAT output
Latency: < 100 μs deterministic (hardware path)
Without FPGA (MCU path):
ADC → MCU SPI read → RTOS task schedule → Calculate → EtherCAT peripheral
Jitter: 200–500 μs (OS scheduling, interrupts, other tasks)
Result:
- FPGA enables real-time control (active power factor correction, coordinated VFD control)
- MCU-only limited to monitoring (can read data, but can’t close loop with determinism)
Market value: Real-time control capability opens industrial automation market (PLC integration, SCADA)
Cost-Benefit Summary
| Feature | MCU-Only | With FPGA (+$20–25) | Market Impact |
|---|---|---|---|
| Base monitoring | ✅ Works | ✅ Cleaner design | Same market |
| GPS sync (coarse) | ✅ ~10 μs | ✅ < 1 μs (10× better) | Monitoring only |
| Synchrophasor (C37.118) | ❌ Fails spec | ✅ IEEE compliant | +30–40% TAM (utilities) |
| EtherCAT monitoring | ✅ Works | ✅ Works | Same market |
| EtherCAT control | ❌ Too much jitter | ✅ < 100 μs deterministic | +20–30% TAM (automation) |
| Future DSP offload | ❌ No headroom | ✅ Field-upgradable | Insurance |
| COGS impact | $380 | $405 (+6.6%) | — |
| Total TAM | 100% | +50–100% | 500–1000% ROI |
Decision: FPGA is worth it
- 6% COGS increase unlocks 50–100% larger addressable market
- Enables utility synchrophasor applications (high-margin)
- Enables industrial automation control (recurring revenue via PLC integration)
- Provides architectural simplicity even without premium features
FPGA Selection: Lattice ECP5
Target: ECP5–17 or ECP5–25 (144-TQFP, 20×20mm)
- Logic: 17k-25k LUTs (comfortable for pass-through + future DSP offload)
- Cost: $14–25 @ qty 50 (depending on density), $12–18 @ qty 1000
- Package: 144-TQFP (same pitch as MCXN947, simplifies PCB routing)
- Qualification: Automotive/industrial grade available
FPGA Alternatives Evaluated
| FPGA | Logic | DSP Blocks | Cost @ qty 50 | Assessment |
|---|---|---|---|---|
| Lattice ECP5–17/25 | 17–25k LUTs | 0 (soft) | $20–25 | ✅ Selected |
| Intel Max 10M08 | 8k LEs | 0 (soft) | $22 | ❌ Too small (tight for DSP offload) |
| Intel Max 10M16 | 16k LEs | 0 (soft) | $28 | ⚠️ $3–8 more expensive than ECP5–17 |
| Xilinx Spartan-7 XC7S15 | 12k cells | 20 DSP48E1 | $20–30 | ❌ Less logic, DSP blocks not needed |
| Xilinx Spartan-7 XC7S25 | 23k cells | 80 DSP48E1 | $30–40 | ❌ Over budget, overkill on DSP |
| Gowin GW2A-18 | 20k LUTs | 48 DSP | $15–20 | 🚩 Supply chain risk (China) |
Why ECP5 Wins
- Best capacity/cost ratio: 17–25k LUTs for $20–25
- No premium for unused DSP: MCU has dual FPU @ 150 MHz (handles all DSP), don’t need hardware DSP blocks
- Supply chain stability: US-based (Lattice), no geopolitical risks
- Toolchain maturity: Diamond (commercial) + prjtrellis (open-source)
- Adequate block RAM: 864 kb (important for FFT buffering if offloaded)
- Low power: 400–500 mW typical (passive cooling sufficient)
Why Not Intel Max 10?
- Max 10M08 ($22): Only 8k LEs, too tight for pass-through (5–7k) + DSP offload (8–12k)
- Max 10M16 ($28): Sufficient logic, but $3–8 more expensive than ECP5–17
- Quartus toolchain excellent, but not worth the premium
Why Not Xilinx Spartan-7?
- DSP48E1 blocks not needed (MCU has hardware FPU, handles all power quality DSP)
- XC7S15 ($20–30): Less logic than ECP5–17, barely in budget
- XC7S25 ($30–40): Over budget (defeats cost advantage)
- Vivado toolchain excellent, but paying premium for DSP blocks we won’t use
Why Not Gowin (Chinese)?
- 🚩 Supply chain risk: China-only manufacturing
- 🚩 Export control risks: US-China tensions (could get blacklisted either direction)
- 🚩 Toolchain maturity: Less proven, weaker documentation
- 🚩 Industrial qualification: Limited automotive/medical certifications
- 🚩 Geopolitical: China 5–10 years behind in FPGA technology (28–55nm vs 7–10nm for US)
China FPGA Status (2025):
- Market share: Gowin ~1%, Anlogic <1% (vs Xilinx 50%, Intel 30%, Lattice 10%)
- Technology node: 28–55nm (vs 7–10nm for US leaders)
- Strategy: Import substitution for low-end domestic use, not competing in high-performance
- Not ahead: 5–10 years behind in architecture IP, EDA tools, and process technology
Implementation Phases
Phase 1: Pass-Through Architecture (v2.0 Launch)
Purpose: Minimize development risk, accelerate time-to-market
FPGA Functions:
- SPI interface management (read ADC data from 3× AMC131M03)
- Data buffering and streaming to MCU
- Digital Rogowski integration (real-time)
- Event trigger logic (voltage sag/swell, overcurrent, frequency deviation)
- GPIO expansion for optional modules (GPS, EtherCAT)
LUT usage estimate: ~5–7k LUTs (leaves 10–18k for future expansion)
DSP on MCU: All power quality calculations performed on dual-core MCXN947
- Core 1: Network/communications
- Core 2: FFT, harmonic analysis, RMS calculations, power/energy
Phase 2: DSP Offload (v2.1+ Firmware Update)
When MCU reaches compute limits, migrate heavy DSP to FPGA:
- FFT computation (per-cycle or 200ms windows)
- Harmonic extraction (50 harmonics × 7 channels)
- RMS sliding window calculations
- Adaptive filtering (noise rejection)
LUT usage estimate: Additional 8–12k LUTs for FFT/DSP blocks
Benefit: Field-upgradable performance improvement without hardware changes
Summary
Lattice ECP5 FPGA selected based on:
- Best cost/performance ratio ($20–25 for 17–25k LUTs)
- Enables premium features (synchrophasor, real-time control)
- Unlocks 50–100% larger addressable market
- Supply chain stability (US-based)
- Architectural simplicity for base system
- Field-upgradable DSP offload capability
Trade-off: 6% COGS increase justified by 500–1000% ROI through market expansion.
Document Status: Final design decision Last Updated: November 2025 Next Review: After alpha prototype validation (Feb 2026)
© 2026 EQ Systems Inc.